1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device including a self-aligned polysilicon layer having no seam or void therein.
2. Description of the Related Art
Semiconductor devices are generally divided into volatile semiconductor devices, such as dynamic random access memory (DRAM) devices or static random access memory (SRAM) devices, and non-volatile semiconductor devices like a read only memory (ROM) devices. Volatile semiconductor devices have a relatively high response speed; however, data stored therein may be lost with the lapse of time. Although non-volatile semiconductor devices permanently store data therein, such devices have a relatively low response speed.
Recently, non-volatile semiconductor devices such as flash memory devices or electrically erasable and programmable ROM (EEPROM) devices have been widely used in various electronic apparatuses. In flash memory devices, data may be electrically stored and/or read out from memory cells of the flash memory devices by employing either the Flower-Nordheim tunneling effect or hot carrier injection effect. Flash memory devices are typically divided into a NAND type memory device and a NOR type memory device. In the NAND type memory device, a plurality of cell transistors is serially connected to form unit strings and the unit strings are connected in parallel to a bit line and a ground line. In the NOR type memory device, each of the cell transistors is electrically connected in parallel between a bit line and a ground line. Both have their respective advantages: the NAND type memory device may have a relatively high response speed, while the NOR type memory device has a relatively high integration.
Memory cells used in flash memory devices typically have a vertically stacked gate structure that includes a floating gate formed on a silicon substrate. The stacked gate structure generally has at least one tunnel oxide layer or dielectric layer, and a control gate formed on or near the floating gate. In the memory cell of the NAND type memory device, a plurality of floating gates is formed in an active region having a line shape. Here, the floating gates are intended to be exactly formed at predetermined portions of the active region. However, due to decreasing design rules, the floating gates may not be precisely formed at the predetermined portions of the active region due to the active region's greatly reduced size. That is, the critical dimensions of the floating gate decrease much more quickly than the design rules for flash memory devices as a whole.
To solve the above-mentioned problem, there has been developed a method of forming a floating gate including a self-aligned polysilicon (SAP) layer. In this method, after an opening is formed through an isolation layer, a polysilicon layer is formed to fill up the opening, thereby forming the floating gate. However, poor step coverage may cause the polysilicon layer to not completely fill up the opening when the opening, thereby forming a seam in the polysilicon layer. This seam formation problem is further exacerbated by the fact that openings formed through the isolation layer generally have an upper portion relatively narrower than a lower portion thereof.
FIG. 1 is a cross sectional view illustrating a seam generated in a polysilicon layer for a floating gate of a conventional flash memory device.
As shown in FIG. 1, a seam 12 is inadvertently formed in a polysilicon layer 10 when filling the opening formed through an isolation layer 15. This seam might not be completely removed in a subsequent process for forming a floating gate, therefore resulting in an undesired electrical effect. That is, oxide may form in the seam 12 in a successive process thereby degrading the electrical characteristics of the flash memory device.